In semiconductor devices, such as a Dynamic Random Access Memory (DRAM) device, the transistor gates are predominantly made of polysilicon and an overlying conductive layer, such as titanium silicide or tungsten silicide. However, tungsten silicide and titanium silicide are larger grain materials that contribute to a rough silicide/silicon interface, which increases the resistance of the transistor gate stack.
Recent semiconductor fabrication methods have been developed to incorporate other types of metal silicide, such as cobalt silicide or nickel silicide, which are smaller grained materials than the titanium silicide or tungsten silicide materials. However, due to the difficulty of etching smaller grained sized metal silicide, these metal suicides can be difficult to incorporate into current fabrication techniques. For example, one technique is demonstrated in prior art FIG. 1-5.
As shown in FIG. 1, layers of material to build a transistor gate stack are formed on silicon substrate 10. First gate oxide 11 is formed, followed in sequence by the formation of polysilicon layer 12, titanium or titanium nitride (Ti/TiN) layer 13, cobalt layer 14, silicon layer 15, nitride layer 16 and finally a pattern photoresist 17.
As shown in FIG. 2, an etch is performed to begin forming the transistor gate stack by patterning nitride 16, silicon 15 and stopping on cobalt layer 14. Silicon 15 is forced to react with cobalt layer 14 where they come into contact with each other to form the cobalt silicide region 30 as seen in FIG. 3. Because this reaction will also occur isotropically (in both the vertical and horizontal directions), cobalt silicide region 30 expands outside the bounds of the original gate stack pattern (defined by nitride 16). As shown in FIGS. 4 and 5, two additional etches are required to complete the transistor gate stack, one wet etch to remove the cobalt material outside the gate stack and one to pattern Ti/TiN layer 13, polysilicon 12 and gate oxide 11. However, the cobalt silicide region 30 will not be affected by the current etch chemistries used to complete the transistor gate stack and thus increases the width of the gate stack.
Therefore, the above method requires several etching steps, increases the critical dimension of the device feature sizes and possibly increases the resistance of the transistor gate stack as the method requires sufficient silicon 15 to ensure that all of the cobalt is converted to cobalt silicide during the reaction step, which in all likelihood results in a small amount of silicon to remain in the gate stack and thus increases the resistance of any contact to this stack.
Currently, in semiconductor fabrication, there is a need for a method to form a metal silicide component of a transistor gate, without increasing the contact resistance or feature size of the device, that will also allow the integration of a transistor gate capping layer that can be used to form the gates of both n-channel and p-channel transistors in semiconductor devices, a need of which is addressed by the following disclosure of the present invention that will become apparent to those skilled in the art.